k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 1 document title 32kx8 bit low power and low voltage cmos static ram revision history revision no. 0.0 1.0 1.01 remark preliminary final final history initial draft finalize - add 70ns part in km62u256d family - show i cc read only, and increased value i cc = 2ma ? i cc read = 5ma - seperate i cc1 read and write i cc1 = 5ma ? i cc1 read = 5ma, i cc1 write = 10ma - improved standby current(i sb1 ) commercial part: 10 m a ? 5 m a extended and industrial part: 20 m a ? 5 m a - improved v il (min.): 0.4v ? 0.6v - improved power dissipation: 0.7w ? 1w errata correction - removed ?ttl compatible? from features - errata correction from 4.5v to 3.0/2.7v for data retention wave form draft data april 1, 1997 november 12, 1997 october 24, 2001 the attached datasheets are provided by samsung electronics. samsung electronics co, ltd. reserve the right to change the specif ications and products. samsung electronics will answer your questions about device. if you have any questions, please contact the samsung bra nch offices.
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 2 32kx8 bit low power and low voltage cmos static ram general description the k6t0808v1d and k6t0808u1d families are fabricated by samsung's advanced cmos process technology. the families support various operating temperature range and have various package types for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features ? process technology: 0.4 m m cmos ? organization: 32kx8 ? power supply voltage k6t0808v1d family: 3.0~3.6 v k6t0808u1d family: 2.7~3. 3v ? low data retention voltage: 2v(min) ? three state outputs ? package type: 28-sop-450, 28-tsop1-0813.4f/r product family 1. the parameter is measured with 30pf test load. 2. k6t0808v1d family support sop package without 100ns speed bin. product family operating temperature v cc range speed power dissipation pkg type standby (i sb1 , max) operating (icc 2 , max) k6t0808v1d-b commercial(0~70 c) 3.0v ~3.6v 70 1) /100ns 5 m a 35ma 28-sop-450 2) 28-tsop1-0813.4f/r k6t0808u1d-b 2.7v ~ 3.3v 70 1) /85/100ns k6t0808v1d-d extended(-25~85 c) 3.0v ~3.6v 70 1) /100ns k6t0808u1d-d 2.7v ~ 3.3v 70 1) /85/100ns k6t0808v1d-f industrial(-40~85 c) 3.0v ~3.6v 70 1) /100ns k6t0808u1d-f 2.7v ~ 3.3v 70 1) /85/100ns samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description pin name function pin name function a 0 ~a 14 address inputs i/o 1 ~i/o 8 data inputs/outputs we write enable input vcc power cs chip select input vss ground oe output enable input nc no connect functional block diagram a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 28-sop 15 16 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a11 a9 a8 a13 we vcc a3 a14 a12 a7 a6 a5 a4 a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 28-tsop type1 - forward 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 28 25 24 23 22 21 20 19 18 17 16 15 oe 28-tsop a11 a9 a8 a13 we vcc a3 a14 a12 a7 a6 a5 a4 a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 28 25 24 23 22 21 20 19 18 17 16 15 oe type1 - reverse precharge circuit. memory array 256 rows 128 8 columns i/o circuit column select clk gen. row select a10 a3 a0 a1 a2 a11 a9 a13 a8 a12 a14 a4 a5 a7 cs we i/o 1 data cont data cont oe i/o 8 a6 control logic
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 3 product list commercial temp. product (0~70 c) extended temp. products (-25~85 c) industrial temp products (-40~85 c) part name function part name function part name function k6t0808v1d-gb70 k6t0808v1d-tb70 k6t0808v1d-tb10 k6t0808v1d-rb70 k6t0808v1d-rb10 k6t0808u1d-gb70 k6t0808u1d-gb85 k6t0808u1d-gb10 k6t0808u1d-tb70 k6t0808u1d-tb85 k6t0808u1d-tb10 k6t0808u1d-rb70 k6t0808u1d-rb85 k6t0808u1d-rb10 28-sop, 70ns, 3.3v 28-tsop-f, 70ns, 3.3v 28-tsop-f, 100ns, 3.3v 28-tsop-r, 70ns, 3.3v 28-tsop-r, 100ns, 3.3v 28-sop, 70ns, 3.0v 28-sop, 85ns, 3.0v 28-sop, 100ns, 3.0v 28-tsop-f, 70ns, 3.0v 28-tsop-f, 85ns, 3.0v 28-tsop-f, 100ns, 3.0v 28-tsop-r, 70ns, 3.0v 28-tsop-r, 85ns, 3.0v 28-tsop-r, 100ns, 3.0v k6t0808v1d-gd70 k6t0808v1d-td70 k6t0808v1d-td10 k6t0808v1d-rd70 k6t0808v1d-rd10 k6t0808u1d-gd70 k6t0808u1d-gd85 k6t0808u1d-gd10 k6t0808u1d-td70 K6T0808U1D-TD85 k6t0808u1d-td10 k6t0808u1d-rd70 k6t0808u1d-rd85 k6t0808u1d-rd10 28-sop, 70ns, 3.3v 28-tsop f, 70ns, 3.3v 28-tsop f, 100ns, 3.3v 28-tsop r, 70ns, 3.3v 28-tsop r, 100ns, 3.3v 28-sop, 70ns, 3.0v 28-sop, 85ns, 3.0v 28-sop, 100ns, 3.0v 28-tsop-f, 70ns, 3.0v 28-tsop-f, 85ns, 3.0v 28-tsop-f, 100ns, 3.0v 28-tsop-r, 70ns, 3.0v 28-tsop-r, 85ns, 3.0v 28-tsop-r, 100ns, 3.0v k6t0808v1d-gf70 k6t0808v1d-tf70 k6t0808v1d-tf10 k6t0808v1d-rf70 k6t0808v1d-rf10 k6t0808u1d-gf70 k6t0808u1d-gf85 k6t0808u1d-gf10 k6t0808u1d-tf70 k6t0808u1d-tf85 k6t0808u1d-tf10 k6t0808u1d-rf70 k6t0808u1d-rf85 k6t0808u1d-rf10 28-sop, 70ns, 3.3v 28-tsop f, 70ns, 3.3v 28-tsop f, 100ns, 3.3v 28-tsop r, 70ns, 3.3v 28-tsop r, 100ns, 3.3v 28-sop, 70ns, 3.0v 28-sop, 85ns, 3.0v 28-sop, 100ns, 3.0v 28-tsop-f, 70ns, 3.0v 28-tsop-f, 85ns, 3.0v 28-tsop-f, 100ns, 3.0v 28-tsop-r, 70ns, 3.0v 28-tsop-r, 85ns, 3.0v 28-tsop-r, 100ns, 3.0v functional description 1. x means don't care (must be in high or low states) cs oe we i/o mode power h x 1) x 1) high-z deselected standby l h h high-z output disabled active l l h dout read active l x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to v cc +0.5 v - voltage on vcc supply relative to vss v cc -0.5 to 4.6 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t0808v1d-b, k6t0808u1d-b -25 to 85 c k6t0808v1d-d, k6t0808u1d-d -40 to 85 c k6t0808v1d-f, k6t0808u1d-f soldering temperature and time t solder 260 c, 10sec (lead only) - -
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 4 recommended dc operating conditions 1) note: 1. commercial product: t a =0 to 70 c, otherwise specified industrial product: t a =-40 to 85 c, otherwise specified 2. overshoot: v cc +3.0v in case of pulse width 30ns 3. undershoot: -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested item symbol product min typ max unit supply voltage vcc k6t0808v1d family 3.0 3.3 3.6 v k6t0808u1d family 2.7 3.0 3.3 ground vss all 0 0 0 v input high voltage v ih k6t0808v1d, k6t0808u1d family 2.2 - vcc+0.3 v input low voltage v il k6t0808v1d, k6t0808u1d family -0.3 3) - 0.6 v capacitance 1) (f=1mhz, ta=25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il , v io =v ss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs =v il, v in =v ih or v il , read - 2 5 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma cs 0.2v, v in 0.2v, v in 3 vcc -0.2v read - 1.5 5 ma write - 6 10 i cc2 cycle time=min,100% duty, i io =0ma, cs =v il, v in =v ih or v il - 23 35 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs =v ih , other inputs = v il or v ih - - 0.3 ma standby current (cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc - 0.1 5 m a
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 5 c l 1) 1. including scope and jig capacitance test conditions (test load and test input/output reference) input pulse level: 0.4 to 2.4v input rising and falling time: 5ns input and output reference voltage: 1.5v output load (see right): c l =100pf+1ttl c l 1) =30pf+1ttl 1. refer to ac characteristics ac operating conditions ac characteristics (k6t0808v1d family: vcc=3.0~3.6v, , k6t0808u1d family: vcc=2.7~3.3v commercial product: t a =0 to 70 c, extended product: t a =-25 to 85 c, industrial product: t a =-40 to 85 c) 1. the parameter is measured with 30pf test load parameter list symbol speed bins units 70 1) ns 85ns 100ns min max min max min max read read cycle time t rc 70 - 85 - 100 - ns address access time t aa - 70 - 85 - 100 ns chip select to output t co - 70 - 85 - 100 ns output enable to valid output t oe - 35 - 40 - 50 ns chip select to low-z output t lz 10 - 10 - 10 - ns output enable to low-z output t olz 5 - 5 - 5 - ns chip disable to high-z output t hz 0 30 0 30 0 35 ns output disable to high-z output t ohz 0 30 0 30 0 35 ns output hold from address t oh 5 - 10 - 15 - ns write write cycle time t wc 70 - 85 - 100 - ns chip select to end of write t cw 60 - 70 - 80 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 60 - 70 - 80 - ns write pulse width t wp 50 - 60 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 25 0 25 0 35 ns data to write time overlap t dw 30 - 35 - 40 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 5 - 10 - 10 - ns data retention characteristics item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 2.0 - 3.6 v data retention current i dr vcc=3.0v, cs 3 vcc-0.2v - 5 m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 6 address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs address oe data ou t notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oh t aa t olz t lz t ohz t hz t rc t oe t co
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 7 timing waveform of write cycle(2) ( cs controlled) address cs t wc t wr(4) t as(3) t dw t dh data valid we data in data out high-z high-z t cw(2) t wp(1) t aw notes (write cycle) 1. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low : a write end at the earliest transition among cs going high and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. data retention wave form cs controlled v cc 3.0v/2.7v 1) 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(1) ( we controlled) address cs t cw(2) t wr(4) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t wc t aw t as(3) 1. 3.0v for k6t0808v1d family, 2.7v for k6t0808u1d family
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 8 package dimensions units: millimeter(inch) 28 pin plastic small outline package(450mil) 0~8 #28 11.81 0.30 0.465 0.012 18.29 0.20 0.720 0.008 max 18.69 0.736 max 2.59 0.20 0.102 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #15 0.41 0.10 0.016 0.004 #1 #14 0.89 ( ) 0.035 1 1 . 4 3 0 . 4 5 0 8.38 0.20 0.330 0.008 1.02 0.20 0.040 0.008 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 1.27 0.050
k6t0808v1d, k6t0808u1d family cmos sram revision 1.01 october 2001 9 package dimensions 28 pin thin small outline package type1 (0813.4f) #28 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 m a x 0 . 1 0 m a x #1 13.40 0.20 0.528 0.008 #15 #14 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.55 0.0217 0.425 ( ) 0.017 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 #28 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 m a x 0 . 1 0 m a x #1 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 13.40 0.20 0.528 0.008 #15 #14 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 0.425 ( ) 0.017 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 0.55 0.0217 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 28 pin thin small outline package type1 (0813.4r) 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 typ 0.25 0.010 units: millimeter(inch)
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